Simulating the delay in logic networks for large, high-speed computers
نویسنده
چکیده
When designing a computer with TTL logic circuits, the delays of logic paths have been estimated by considering the number of gate delays and adding in load and media factors. Such a simplistic approach is not accurate enough for calculating delays when designing high-performance large systems using high-speed, non-saturating circuits such as HCML (Honeywell's Current Mode Logic). There are several reasons:
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تاریخ انتشار 2010